1. Field of the Invention
The present invention relates to data output circuits integrated within LSIs, such as data output buffer circuits. More specifically, the present invention relates to data output circuits suitable for outputting data on transmission lines through connection slots.
2. Description of the Related Art
The progress in semiconductor technologies has enhanced the use of high-performance computers in various applications. Computers are necessarily designed to be suitable for users' purposes. One approach for improving suitability of computers for users' purposes is to incorporate a set of CPU boards, each used for data processing, on a backplane board in a computer system, as disclosed in Japanese Laid-Open Patent Application No. H08-6676A.
In order to achieve high-speed operation, high speed data transmission is required in the computer system. This necessitates high transmitting speed through data transmission lines on the backplane board, and high operation speed of data output circuits disposed on CPU boards.
Such circumstances require data output circuits to incorporate high-speed, low-power consumption MOS (Metal Oxide Semiconductor) transistors. Such MOS transistors are often required be operated on the low power voltage. Although exhibiting high operation speed, low-voltage transistors suffer from inferior endurance against the overvoltage and surge. Therefore, overvoltage and surge protection is an important issue for a CPU board incorporating data output circuits composed of low-voltage transistors.
FIG. 1 is a circuit diagram showing a typical structure of a conventional data output circuit. Referring to FIG. 1, the data output circuit includes a pair of differential transistors: NMOS transistors 101 and 102. Sources of the NMOS transistors 101 and 102 are connected to a drain of an NMOS transistor 103 through a node 111. The NMOS transistor 103 functions as a constant-current source operating on a bias Vs1 applied to the gate. The source of the NMOS transistor 103 is connected to the ground line gnd.
A drain of the NMOS transistor 101 is connected to an output terminal OUTB and a resistor 105 through a node 113, while a drain of the NMOS transistor 102 is connected to an output terminal OUT and a resistor 106 through a node 114. The resistors 105 and 106 are connected to a drain of a PMOS transistor 104 through a node 112, and the source of the PMOS transistor 104 is connected to a power supply line Vdd. A bias Vc1 is applied to the gate of the PMOS transistor 104, and the PMOS transistor 104 functions as a variable resistor. Here, the power supply line Vdd is provided with a power supply voltage of 3.6V.
Irrespective of the fact that 3.6V is supplied as the power supply voltage, low-voltage transistors typically have a rated operation voltage of 1.3V, and an absolute maximum rating of 1.6V. In the conventional data output circuit, low-voltage transistors are used as the NMOS transistors 101 and 102 and the NMOS transistor 103 for achieving high-speed operation.
In a normal operation of the data output circuit shown in FIG. 1, the voltage between the drain and the gate of the NMOS transistor 101 is equal to or less than the rated operation voltage, that is, 1.3V, when the “Low” level (0V) is developed on the input IN, and the “High” level (1.3V) is developed on the input INB. In some cases, however, an overvoltage may be applied to the output terminal OUT (or the output terminal OUTB) when the CPU board is pulled out from the backplane board without cutting off the power supply of the backplane board. This undesirably causes the voltage between the drain and gate of the NMOS transistor 101 to exceed the absolute maximum rating of 1.6V of the NMOS transistor 101. For example, the voltage between the drain and gate of the NMOS transistor 101 is increased up to 1.8V when a voltage of 1.8V is externally supplied to the output terminal OUTB with the input IN pulled down to the “Low” level (0V)”. This undesirably causes an overvoltage to be applied to the NMOS transistor 101, and may result in undesirable failure of the NMOS transistor 101 through the gate-oxide breakdown. Additionally, due to the limitation of the rated operation voltage of the low-voltage transistors, the data output circuit shown in FIG. 1 can not output signal levels over the rated operation voltage of the NMOS transistors 101 and 102 even during the normal operation; this undesirably restricts the use of the data output circuit.
The use of high-voltage MOS transistors, such as multi-oxide transistors, for the NMOS transistors 101 and 102 within the data output circuit shown may achieve effective overvoltage and surge protection; however, this undesirably hinders high speed operation of the data output circuit due to the reduced gain of the high-voltage transistors. Additionally, the use of high-voltage transistors for the NMOS transistors 101 and 102 undesirably prohibits the data output circuit from outputting signals of low DC levels. Further, the use of high-voltage transistors undesirably necessitates a high power supply voltage to allow the data output circuit to operate at high speed.
In order to protect the NMOS transistors 101 and 102, as shown in FIG. 2, high-voltage transistors 201, and 202 may be cascade-connected to the NMOS transistors 101 and 102, respectively. The gates of the high-voltage transistors 201, and 202 is provided with a fixed bias Vc2. The data output circuit of FIG. 2 achieves overvoltage and surge protection using the cascade-connected high-voltage transistors 201, and 202.
The data output circuit of FIG. 2, however, undesirably requires an increased size for the high-voltage transistors 201, and 202; in order to avoid the gain being decreased, the high-voltage transistors 201, and 202 are undesirably required to have an increased gate width. This prohibits the high-speed operation of the data output circuit due to the increased parasitic capacitance of the high-voltage transistors 201, and 202.